1. Field of the Invention
This invention relates to a peripheral bus jumper block for linking independent peripheral bus signal traces on a peripheral bus panel to which different arrays of peripheral devices are respectively coupled within a peripheral device enclosure so that all of the peripheral devices can be chained together and operated from the same computer peripheral controller. By virtue of the foregoing, an end user will be able to selectively reconfigure the peripheral bus interconnect system after the peripheral device enclosure has left the manufacturer.
2. Background Art
As will be recognized by those skilled in the computer hardware field where one or more computers controls a plurality of computer peripherals, a peripheral bus interconnect system links the computers to different peripheral devices. The peripheral devices, such as a CD drive, a DVD drive, a hard disk drive, and the like, are commonly housed in a peripheral device enclosure. A typical peripheral bus system, such as that just described, is illustrated in FIG. 1 of the drawings, where a computer is shown interfaced with a single array of computer peripheral devices 3-1, 3-2, 3-3 . . . 3-n that are all housed within a single port peripheral device enclosure 5. The peripheral bus interconnect system includes first and second cable sections 7 and 9 that couple the computer 1 to the peripheral devices 3 within enclosure 5.
More specifically, the first cable section 7 of the peripheral bus interconnect system is detachably connected between an output peripheral bus connector 10 of the computer 1 and an input bus connector 12 of the peripheral device enclosure 5. The second cable section 9 of the peripheral bus interconnect system is internal to the peripheral bus enclosure 5 and runs between the input connector 12 thereof and a cable terminator 14. The cable terminator 14 is located at the end of cable section 9 either outside (as shown) or inside the enclosure 5. Each of the peripheral devices 3 is coupled to the internal cable section 9 (e.g., either directly or by way of bus transceivers). In the configuration illustrated in FIG. 1, the computer 1 has a single peripheral controller (not shown) by which each of the peripheral devices 3 that is located within the peripheral device enclosure 5 is operated to receive data and control signals by way of the first and second cable sections 7 and 9.
The difficulty with the peripheral bus interconnect system illustrated in FIG. 1 is that the end user can do little to reconfigure the cable section 9 within peripheral device enclosure 5 once the enclosure has left the manufacturer. Thus, all of the peripheral devices 3 that are coupled to the cable section 9 within enclosure 5 are driven by the same peripheral controller of the computer. The operation and control of all of the peripheral devices 3 from the same controller may not be desirable in all instances and, consequently, limits the flexibility of the peripheral device enclosure 5 within which the peripheral bus interconnect system is located.
To overcome the problem with the non-configurable system shown in FIG. 1, the peripheral bus interconnect system shown in FIG. 2 of the drawings has sometimes been adopted. In this case, a computer 20 is interfaced with first and second arrays of computer peripheral devices 23-1, 23-2, 23-3 . . . 23-n and 24-1, 24-2, 24-3 . . . 24-n that are housed within a dual port peripheral device enclosure 25. The arrays of peripheral devices 23 and 24 within peripheral device enclosure 25 are now interfaced with the computer by means of a pair of peripheral buses.
A first of the pair of peripheral buses having first and second cable sections 27 and 29 couples the computer 20 to the first array of peripheral devices 23 within enclosure 25. The first cable section 27 of the first peripheral bus is detachably connected between a first output peripheral bus connector 30 of computer 20 and a first input bus connector 32 of the dual port peripheral device enclosure 25, and the second cable section 29 is internal to the enclosure 25 and runs between input connector 32 and a cable terminator 34. Each of the peripheral devices 23 of the first array is coupled to the internal cable section 29.
The second of the pair of peripheral buses also has first and second cable sections 36 and 38 to couple the computer 20 to the second array of peripheral devices 24 within enclosure 25. The first cable section 36 of the second peripheral bus is detachably connected between a second output peripheral bus connector 40 of computer 20 and a second input bus connector 42 of the dual port peripheral device enclosure 25, and the second cable section 38 is internal to the enclosure 25 and runs between input connector 42 and a cable terminator 44. Each of the peripheral devices 24 of the second array is coupled to the internal cable section 38. The cable terminators 34 and 44 for the first and second peripheral buses of the peripheral bus interconnect system shown in FIG. 2 are, for example, located internally of the peripheral device enclosure 25.
In the configuration shown in FIG. 2, the computer 20 has a pair of peripheral controllers (not shown) by which to independently control the first and second arrays of peripheral devices 23 and 24 via the first and second peripheral buses which are independently connected to the first and second output peripheral bus connectors 30 and 40. In this same regard, it is also known to replace the computer 20 of FIG. 2 having a pair of peripheral controllers with a pair of computers (not shown), each having a single controller for selectively controlling the arrays of peripheral devices 23 and 24 via the respective first and second peripheral buses.
In either case, the use of the dual port peripheral device enclosure 25 of FIG. 2 to be interconnected to different peripheral controllers allows independent control of the first and second arrays of computer peripheral devices 23 and 24. Nevertheless, it is not possible to interrupt or link the cable sections 29 and 38 of the first and second peripherals buses located within enclosure 25 to which the different arrays of peripheral devices 23 and 24 are coupled. That is, the end user cannot reconfigure the peripheral bus interconnect system of FIG. 2 so as to be able to operate both arrays of peripheral devices 23 and 24 from the same peripheral controller.
Disclosed below is a peripheral bus jumper block to be used for linking independent peripheral bus signal paths (e.g., traces) from a peripheral bus interconnect system to which different arrays of computer peripheral devices are coupled so that all of the peripheral devices can be tied together and operated from the same computer controller. The arrays of peripheral devices are housed within a peripheral device enclosure. Each array of peripheral devices is coupled to a respective peripheral signal path that is formed on a peripheral bus panel within the enclosure.
The peripheral bus jumper block of this invention includes a pair of peripheral bus mating connectors that are carried on a printed circuit board having suitable linking circuitry. The mating connectors of the jumper block are adapted to be respectively connected to a pair of peripheral bus panel connectors that are accessible at the peripheral bus panel within the peripheral device enclosure and communicate with the independent signal paths to which a pair of arrays of peripheral devices are coupled. By connecting more than one jumper block to different pairs of peripheral bus panel connectors, a plurality of independent signal paths of the peripheral bus interconnect system can be quickly and easily chained together on the bus panel within the peripheral device enclosure so that different arrays of peripheral devices can be operated from the same computer controller. By virtue of the foregoing, the end user may effectively configure the peripheral bus interconnect system after the peripheral device enclosure has left the manufacturer to selectively operate any desired number of arrays of peripheral devices.
When a peripheral bus jumper block is connected to a pair of peripheral bus panel connectors, at least one pin connection therebetween carries a signal that is dedicated to providing an indication when the peripheral bus interconnect system is operating in a single segment mode, as described above. That is, the connection of the jumper block causes the dedicated signal to experience a decrease in voltage. An analog to digital converter is responsive to the voltage decrease to transmit a corresponding digital signal to a processor located within the peripheral device enclosure by which to indicate to an external computer the chaining of a pair of peripheral bus signal paths and the linking of the peripheral devices coupled thereto.